PROGRAM| SPEAKERS| SPONSORSHIP | WINNERS| GALLERY
Past Program Schedule
DAY 1| DAY 2| DAY 3*All Times are in Mountain Standard Time (MST, UTC−07:00; 24-hour format)
Time
Day 1: October 27, 2026
07:30 – 08:30
Registration & Breakfast
08:30 – 08:45
Opening Remarks & Awards
PLENARY SESSION I
Chair: Will Zortman – Sandia National Labs
08:45 – 09:15
Keynote Talk I: Digital Twin Optimized Composable Systems - Enabling SOTA Intel Technologies in USG Systems
Dr. Carl E. McCants – Principal Engineer, Microelectronics SME | Intel Corporation
09:15 – 09:35
Visionary Talk 1: Advanced Packaging for Photonics
Dr. Charles Woychik – VP Sales and Marketing | NHanced Semiconductors, Inc.
09:35 – 10:00
Break
SESSION I: Invited Talks
Chair: Mari-Therese Burton – ARMY
10:00 – 10:20
METIS: Data Ecosystem for CHIPS Metrology
Dr. June Lau – Physicist and Data Specialist | NIST
10:20 – 10:40
From Research to Impact: Technology, Talent & Teamwork in the SRC Ecosystem
Girish Wable – Director - Technical Program and Memberships | Semiconductor Research Corporation (SRC)
10:40 – 11:00
Fast, Multi-Scale 3D X-Ray Inspection of Intact PCBs
Jeff Gelb – Director | Applied Materials, X-Ray Control Technologies
11:00 – 11:20
Evaluation Approaches for Advanced Heterogeneous Packaging
Ruth Hidalgo-Hernandez – Technical Leader | DOD
Aaron Clough-Paez – Technical Leader | DOD
11:20 – 11:40
Evolving Technique and Application Challenges in Thermal Warpage Metrology
Neil Hubble – President | AkroMetrix, LLC
11:40 – 12:50
Lunch
PLENARY SESSION II
Chair: Dr. Adam Kimura – Battelle Memorial Institute
12:50 – 13:20
Keynote Talk II: Beyond the Fab: Building Arizona’s Semiconductor Talent and Partnership Pipeline
Dr. Kyle Squires – Senior Vice Provost of Engineering, Computing and Technology; Vice Provost of the Polytechnic Campus; Dean, Fulton Schools of Engineering | Arizona State University
SESSION II: Panel Discussion
Moderator: Dr. Wayne Churaman – CTEA Secure Edge/IoT, Microelectronics Commons
13:20 – 14:50
Secure Edge
Daniel Marrujo – President and Managing Director | Trusted Strategic Solutions, LLC
Tony Trinh – Senior Director, Advanced Concepts | Mercury Systems
Dr. Yong Kim – AFRL
Dr. Carl E. McCants – Principal Engineer, Microelectronics SME | Intel Corporation
14:50 – 15:10
Break
SESSION III: Paper Presentations
Chair: Dr. Calvin Chan – Sandia National Labs
15:10 – 15:30
Quality Inspection of Printed Circuit Board Pin Insertion via Semantic Segmentation and Board-Level Feature Extraction
Nils Rabeneck – Technical University of Applied Sciences Regensburg
15:30 – 15:50
PINN Framework for X-ray Laminography Inspection and Reconstruction
Shajib Ghosh – University of Florida
15:50 – 16:10
Towards a framework for evaluating X-ray based volumetric image segmentation
Dr. Felix Kim – NIST
16:10 – 16:30
PatchGuard Lacks Robustness: Breaking State-Of-The-Art Defect Detection Under New Norm Attacks
Kaleel Mahmood
16:30 – 17:30
Exhibit & Poster Session
17:30 – 19:30
Social Event
Time
Day 2: October 28, 2026
07:00 – 08:00
Breakfast
PLENARY SESSION III
Chair: Dr. Adam Waite – Battelle Memorial Institute
08:00 – 08:25
Keynote Talk III: The Future of DoW Microelectronics
Eric Makara – Program Manager for Microelectronics | Office of the Under Secretary of War for Research and Engineering, OUSW (R&E)
08:25 – 08:50
Keynote Talk IV: Enabling Massive Contour-Based Metrology in the Angstrom Era
Dr. Chih-Hung Max Hsieh – Senior Product Manager | Siemens EDA
SESSION IV: Panel Discussion
Moderator: David Via – Director of CONNECT Platform | Midwest Microelectronics Consortium (MMEC)
08:50 – 10:00
Next-Gen Metrology & Inspection: Bridging NIST Science and Semiconductor Innovation
Dr. Jason Killgore – NIST
Dr. Felix Kim – NIST
Dr. Nathan Nakamura – NIST
Dr. Marty Stevens – NIST
Matt Walsh – Chief Engineer, Business Development Director | Florida Semiconductor Engine
Dr. Eyal Weiss – Founder & CTO | Cybord
10:00 – 10:20
Break
SESSION V: Invited Talks
Chair: Christian Eakins – Air Force Research Lab
10:20 – 10:40
Failure Observation and Reliability Evaluation via Scalable Imaging for Heterogeneous Technologies
Dr. Darren Crum – Director of Microelectronics Lab | Purdue Applied Research Institute
10:40 – 11:00
Analog AI for Reliability
Dr. Rong Pan – Professor | School of Computing and Augmented Intelligence, Arizona State University
11:00 – 11:20
Classification of Defects in Tomographic Reconstructions of Hyperscale Advanced Packages
Dr. Jacob D. Rezac – Mathematical Statistician | NIST
11:20 – 11:40
Embedded Mixed Signal Test and Reliability Monitoring in Biomedical Electronics
Christian Gil Ramiscal – Technical Staff Engineer | Microchip Technology Inc.
Krishna Pramod Madabhushi – Senior Principal IC Design Engineer | Medtronic
11:40 – 12:00
Advances in Hyperspectral X-ray Imaging for Hardware Verification
Dr. Eric Goodman – Principal Member Technical Staff | Sandia National Laboratories
12:00 – 13:00
Lunch
SESSION VI: Panel Discussion
Moderator: Dr. Erin Gawron-Hyla – Protective Technologies Team Lead | DEVCOM Army Research Laboratory
13:00 – 14:30
Microelectronics Workforce Development
Dr. Debbie Black-Conn – WFD Lead | ME Commons
Dr. Marla L. Dowell – Executive Director, EDGE Consortium | Dartmouth College
Ms. Alex Winslow – NNME Lead | SEMI Foundation
Dr. Peggy Williams – Program Manager, SCALE Workforce Development Program | Naval Surface Warfare Center, Crane Division
SESSION VII: Invited Talks (Short Session)
Chair: Sneha Sudhakaran – Florida Institute of Technology
14:30 – 15:10
Progress in Electrical Metrology for Conducted and Side Channel Measurements
Dr. Nelson Hastings – Cybersecurity and Privacy Applications Group | NIST
Dr. Jim Booth – Guided Wave EM Group Leader | NIST
15:10 – 15:25
Break
SESSION VIII: Paper Presentations
Chair: Dr. Jacob D. Rezac – NIST
15:25 – 15:45
Hardside: Pre-Silicon Side-Channel Analysis on Hardware AES with Deep Learning
Logan Reichling – University of Cincinnati
15:45 – 16:05
Adams Bridge Accelerator: Bridging the Post-Quantum Transition
Mojtaba Bisheh-Niasa – Microsoft
16:05 – 16:25
Using a CCFI Security Scheme on a RISC-V Core to Observe EMFI Effects and Establish Fault Models
Virgile Bouchon – Mines Saint-Etienne
16:25 – 16:45
Side-Channel Assessment of Rijndael_256 Algorithm
Loic Djomo Tchuenkou – Morgan State University
16:45 – 17:00
Break
SESSION IX: Paper Presentations
Chair: Michael Haselm – Sandia National Labs
17:00 – 17:20
A Quantitative Framework for Microelectronics Assurance from Physical Inspection
Dr. Adam Kimura – Battelle Memorial Institute
17:20 – 17:40
Reversing the Clock: Layout-Aware Recovery of Design Intent from Clock Distribution Networks
Sascha Tommasone – TechInsights Inc.
17:40 – 18:00
A Telemetry-Guided DDR/GDDR Screening Framework for AI-Oriented Memory Systems
Cong Xu – University of South Florida
Time
Day 3: October 29, 2026
07:00 – 08:00
Breakfast
PLENARY SESSION IV
Chair: Dr. Kanad Basu
08:00 – 08:30
Keynote Talk V: From Prototyping to Trust: Lifecycle Assurance for Advanced Heterogeneous Integration
Dr. Krishnendu Chakrabarty – Fulton Professor of Microelectronics | Arizona State University
08:30 – 08:50
Break
SESSION X: Invited Talks
Chair: Dr. Jason Killgore – NIST
08:50 – 09:10
Attacking AI with AI: fault injection on edge NPU case study
Jasper van Woudenberg – Senior Principal Security Technologist | Keysight Technologies
09:10 – 09:30
Multiphoton Microscopy - A New Metrology Tool
Dr. Khanh Kieu – Associate Professor of Optical Sciences | The University of Arizona
09:30 – 10:05
IEEE P3164: Security Annotation for Electronic Design Integration (SA-EDI)
Dr. Matthew Areno – Co-Chair of Secure Edge | Midwest Microelectronics Consortium
10:05 – 10:25
Break
SESSION XI: Paper Presentations
Chair: Emily Haines – Battelle Memorial Institute
10:25 – 10:45
Hide and Speak: Cross-Chiplet Covert Channel Attack in Heterogeneously Integrated Processors
Abir Akib – University of Maryland
10:45 – 11:05
Temperature-Triggered Liquid-State Hardware Trojans for Denial-of-Service in a Plastic-Encapsulated Microcontroller
Parth Agarwal – University of Waterloo
11:05 – 11:25
Symbolic Triage of Gate-Level Information-Flow Evidence for Hardware Trojan Analysis
Dhruvakumar Aklekar – University of North Carolina at Charlotte
11:25 – 11:45
D2D-SLEUTH: S-Parameter Link Evaluation for Unauthorized Tap Hunting
Dan Fiumara – Rensselaer Polytechnic Institute
11:45 – 12:50
Lunch
SESSION XII: Paper Presentations
Chair: TJ Manno – Sandia National Labs
12:50 – 13:10
PCB-QA: Evaluating LLMs over the First Printed Circuit Board Schematic Question-Answer Dataset
Sahana Srinivasan – UNSW Sydney
13:10 – 13:30
Active RF Reflectometry and Machine Learning for Recycled Board Detection
Michael Hilt – University of Waterloo
13:30 – 13:50
PCB-SAGE: LLM-Assisted Security Assessment with Grounded Evidence Across PCB Artifacts
Parsa Mirfasihi – University of Arizona
13:50 – 14:10
Break
SESSION XIII: Paper Presentations
Chair: Dr. Jim Booth – Guided Wave EM Group Leader | NIST
14:10 – 14:30
Encryption using Physical Unclonable Functions
Nikolaos Mastorakis – Arizona State University
14:30 – 14:50
Multi-Angle Specular Constellation Dots for Integrated Circuit Package Authentication
Paul Benedetto – Arizona State University
14:50 – 15:10
MEW-QRC: Physically Unclonable Melt-Electrowritten Quick-Response Codes for Secure Authentication
Neelofar Hassan – New York University
15:10 – 15:30
An AI-Empowered Multidisciplinary Approach to the Detection of Social Engineering Attacks
Joseph M. Hatfield – United States Naval Academy
15:30 – 15:50
Converged Standardization: Improving Template Attack Success Using Aggregated Power Trace Self-Referencing
David Ingalls – Indiana University
15:50 – 16:00
Closing Remarks
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Thanks to our Sponsors
Platinum Sponsors
Gold Sponsors
PAINE 2026 Winners
Best Paper
Metaheuristic Color Scheme Strategies for Enhanced Visual Inspection of 3D IC Layouts
Best Poster
Towards Improving Side-Channel Analysis in FPGAs using the Hardware Response
Gallery
